In the fabrication technologies for semiconductor devices, the packaging of a semiconductor chip is an important step of the total process. The purposes for packaging are several folds, i.e., to provide electrical connection to the chip, to expand the chip electrode pitch for the next level packaging, to protect the chip from mechanical and environmental stresses, and to provide a thermal path for dissipating the heat generated in the chip. The packaging step in the semiconductor manufacturing process affects the overall cost, performance, and reliability of the packaged chip and the system in which the package is used. The performance of a semiconductor device can also be aided by improvements made in the packaging technology. Modern VLSI and ULSI devices require superior packaging performance. A high density ULSI package that contains a relatively large chip requires a smaller external terminal spacing and therefore, further complicates the packaging requirements.
Plastic packages have become more popular as their applications expand into chips that were packaged by hermetically sealed ceramic packages. A plastic package can be produced in a typically automated batch handling process and therefore, can be made very cost competitive. The development in plastic packages has also been aided by the recent improvements in plastic materials, in processing equipment and specific design features that are built into the plastic packages.
In a typical plastic package, a semiconductor chip is attached to the paddle of a lead frame. The lead frame which is made of etched or stamped thin sheet metal serves as a skeleton around which the package can be assembled. The lead frame also provides the external leads in a completed encapsulated package while interconnections are made with fine gold wires. The encapsulation of a plastic package can be carried out in a transfer molding process by using a suitable plastic resin. One of such suitable plastic resin is epoxy or polyimide. The plastic resin covers the chip during the molding process and forms the package's outer dimensions at the same time. The external leads from the lead frame are then formed into a desired shape after the molding process. The benefit of a plastic package is that the plastic thoroughly insulates the chip from its surrounding environment and therefore protects the chip from mechanical and chemical factors outside the chip.
A popularly used plastic package is a plastic quad flat package (PQFP) in which a large number of external leads extend from all four sides of the plastic package after the molding process. It can be economically molded in an automated plastic injection molding process while allowing a maximum number of external leads to be connected to the chip. Variations of the quad flat package have been developed in recent years which include the thin quad flat package (TQFP) and the quad flat J-lead package (QFJ). One of the key requirements in packaging semiconductor chips in a PQFP is the lead integrity, i.e., the co-planarity and skew of the leads. In order to meet a stringent quality control and reliability requirement when a PQFP is assembled to a PC board, the lead configurations on a PQFP must be strictly controlled.
In the quality control and reliability testing of plastic packages equipped with external leads, i.e., such as PQFP's, an optical lead scanner that operates on a CCD (charged couple diode) or laser beam principle is frequently used. The CCD or laser lead scanner has the capability of scanning each of the external leads on a plastic package determining the co-planarity and skewness of each lead. When the measurements on co-planarity and skewness exceed a certain critical value, the packaged IC or the PQFP is rejected. A rejected plastic package can be sent back to its packaging plant where the package can be reworked. In a reworking process, the external leads are first straightened and then reformed into desired configurations according to the specification. Normally, the external leads on a plastic package can be reworked two times before the leads become fragile and susceptible to breakage such that they can no longer be reformed.
In a conventional method for operating a CCD or laser lead scanner, the scanner must first be calibrated by a standard package supplied by the scanner manufacturer to assure its accuracy. A calibration tool is thus required for performing the calibration process. The lead scanner manufacturer frequently supplies a standard package and a software program for use in conjunction with the package for the calibration of the scanner. However, such calibration tool does not always provide the extreme accuracy demanded in modern IC packages. For instance, some of the parameters measured by a lead scanner are in a three dimensional space while the software program supplied can only make planar or two-dimensional corrections. Moreover, the calibration standard supplied by the scanner manufacturer may not provide any resemblance to the actual plastic package measured. For instance, the configuration of a standard calibration sample supplied by the scanner manufacturer, i.e., a 10-pin package can be completely different than the configuration of a PQFP which has 100 pins. These deficiencies greatly reduce the accuracy of the lead scanner when used to measure a high pin-count PQFP.
It is therefore an object of the present invention to provide a calibration standard for use in a lead scanner that does not have the drawbacks and the shortcomings of the conventional calibration standards.
It is another object of the present invention to provide a calibration standard for use in a lead scanner for measuring lead configurations in an IC package that is capable of producing a consistent calibration of the lead scanner.
It is a further object of the present invention to provide a calibration standard for use in an CCD or laser lead scanner for measuring lead configurations in a plastic molded IC package by specially designing three leads on the standard that are longer than the other leads such that a consistent calibration plane can be measured each time the standard is used to calibrate the scanner.
It is another further object of the present invention to provide a calibration standard for use in a CCD or laser lead scanner for measuring lead configurations in an IC package that utilizes three longer leads in the package with one on three of the four sides of the package such that a consistent seating plane can be measured each time by using the standard.
It is yet another object of the present invention to provide a calibration standard for a CCD or laser lead scanner for measuring lead configurations on a PQFP by ensuring that the same three pins on the standard are used for creating a seating plane to improve the consistency and accuracy of the scanner.
It is still another object of the present invention to provide a calibration standard for use in a CCD or laser lead scanner for measuring lead configurations in a PQFP by first providing a consistent seating plane such that readings from the scanner can be calibrated based on such seating plane.
It is yet another further object of the present invention to provide a method for calibrating a lead scanner for measuring lead configurations in an IC package by first providing a calibration standard such that a consistent seating plane can be measured by the scanner for calibrating the scanner and then measuring the deviations of each external leads on the package from such seating plane.
It is still another further object of the present invention to provide a method for calibrating a lead scanner for measuring lead configurations on an IC package by first providing a calibration standard with which the same seating plane can be determined by three specifically designed leads in the package which has a length that is at least 0.03 mm longer than the remaining multiplicity of leads.